The present invention relates to a semiconductor device having a recess channel structure, and more particularly, to a semiconductor device having a recess channel structure in which an adverse affect of a passing gate is reduced, and a method for manufacturing the same.
A reduction in channel length due to a semiconductor device design rule reduction causes a short channel effect in which a threshold voltage is lowered. As a result, an existing planar channel structure reaches a target threshold voltage limit of a transistor. To address this problem, a semiconductor device having a recess channel structure has an increased channel length compared to a semiconductor device having a planar channel structure.
A method for manufacturing a semiconductor device having a conventional recess channel structure will be described hereinafter with reference to attached drawings.
Referring to FIG. 1A, an isolation layer 102 for defining active regions having a gate forming area is formed over a semiconductor substrate 100. A recess mask 104 for exposing the gate forming area is formed over the semiconductor substrate 100 including the isolation layer 102. The recess mask 104 is formed to expose the gate area in the active region as well as a portion of the isolation layer 102 where a gate will pass. A recess 106 is formed by etching the gate area in the active region to a predetermined depth using the recess mask 104 as an etching barrier. The portion A of the isolation layer 102 where the gate will pass is etched to a depth that is less than the depth of the recess in the gate area.
Referring to FIG. 1B, the recess mask is removed. A gate insulation layer 110, a gate conductive layer 112 and a hard mask layer 116 are sequentially formed over the semiconductor substrate 100 including the recess 106. The hard mask layer 116, the gate conductive layer 112 and the gate insulation layer 110 are etched to form gates 120 and 122 over the recess 106. The gates 120 and 122 are formed to have a linear shape over the gate area of the active region formed with the recess 106 as well as the portion of the isolation layer 102 having an undesirably etched depth.
Hereinafter, the gate area of the active region (i.e., the gate 120 arranged over the recess 106) will be referred to as a main gate and the gate 122 arranged over the isolation layer 102 adjacent to the main gate will be referred to as a passing gate.
Source and drain areas 130 and 132 are respectively formed in a storage node contact area and a bit line contact area at both active regions of the main gate 120. A series of known follow up processes are sequentially performed, thereby completing formation of a semiconductor device having a recess channel structure.
In the semiconductor device having the conventional recess channel structure described above, a distance L, between the main gate 120 and the passing gate 122 becomes shortened as shown in FIG. 1B, as the isolation layer is etched when etching the gate forming area. Because the adverse affect of the passing gate 122 on the main gate 120 is increased as the distance L, between the main gate 120 and the passing gate 122 becomes shortened, a reduction in the threshold voltage and an increase in the leakage current in the main gate 120 results. The affect of the passing gate 122 becomes greater with the increased integration of a semiconductor device and should be addressed to improve the performance of a semiconductor device having a recess channel structure.